CORE-V CV32A6-step1 Design Verification Plan Logo
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Contents:

  • Introduction
  • FRONTEND module
CORE-V CV32A6-step1 Design Verification Plan
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CV32A6-step1 Design Verification Plan

Contents:

  • Introduction
    • License
    • Standards Compliance
    • Getting start verification
    • Documentation framework
    • Contributors
  • FRONTEND module
    • PC generation stage feature
      • 001_BTB sub-feature
      • 002_BHT sub-feature
      • 003_RAS sub-feature
      • 004_Return from environment call sub-feature
      • 005_Exception/Interrupt sub-feature
      • 006_Pipeline flush sub-feature
      • 007_Debug sub-feature
      • 008_Address mapping change sub-feature
      • 009_Pc gen priority sub-feature
    • BTB feature
      • 000_flush sub-feature
      • 001_table depth sub-feature
      • 002_Table update sub-feature
      • 003_debug is not intrusive sub-feature
    • BHT feature
      • 000_flush sub-feature
      • 002_table update sub-feature
      • 003_saturation sub-feature
      • 004_Table depth sub-feature
      • 005_Debug is not intrusive sub-feature
    • RAS feature
      • 000_flush sub-feature
      • 001_table depth sub-feature
      • 002_Table update sub-feature
      • 003_Debug is not intrusive sub-feature
    • Instr_realign feature
      • 000_C extension sub-feature
      • 001_Flush sub-feature
    • Instr_queue feature
      • 000_FIFO depth sub-feature
      • 001_Page fault exception sub-feature
      • 002_Flush sub-feature
    • Instr_scan feature
    • Fetch stage feature
      • 001_MMU translation sub-feature
      • 002_Exceptions sub-feature
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